not in a mood to do any thing i dont know why......
the problem is current mirror its not giving the desired output current and the transistors are entering into triode .........
i am not getting the ramp like waveform across the load capacitor where i will get my clock....
the drain voltage is needed to be controlled..............
how to do that??probably the transmission gate widths may need to be changed .............

clock designing is very challenging........
and since it is trapezoidal its a bit tricky too
any how its almost done by using current sources before going home have to design the current mirror kind of ckts........................
going home on 15th
ee sari balu ni meet avali he is very angry i didnt met him when i last went to hyd.....
may be 3 days in hyd 3 days in badhrachalam.....tour to papikondalu
ento intlo andaru full josh.........
planned atour it will be full of fun....
planned by dad its surprise.normally dad says no-no to all these..........
suryapet 3days.......remaining in kmm....probably in kmm 2 days
dnc is not here if he is here then i would have done with all this stuff................